This application is related to co-pending patent application, U.S. Ser. No. 09/490,132 entitled xe2x80x9cFlexible Interrupt Controller That Includes An Interrupt Force Registerxe2x80x9d filed on Jan. 24, 2000 and assigned to the same assignee as the present application.
This application is also related to patent application, U.S. Ser. No. 09/335,105, now U.S. Pat. No. 6,378,022, entitled xe2x80x9cMethod And Apparatus For Processing Interruptible Multi-Cycle Instructionsxe2x80x9d filed on Jun. 17, 1999 and assigned to the same assignee as the present application.
1. Field of the Invention
This invention relates generally to data processing systems, and more specifically, to arbitration of control of communication buses within data processing systems.
2. Background of the Invention
In data processing systems containing multiple communication bus masters, bus arbitration logic is used to select one of several requesting masters to obtain bus ownership. The selection of a bus master may be made using a number of known methods. Examples of existing algorithms used to implement a selection include implementing selection by round robin ordering, selection by fairness or selection by a strict assigned priority. In many data processing systems it is desired for one bus master to hold ownership of a global communication bus for the duration of a burst transfer associated with a cache memory line fill or copyback operation, without any interruption of bus ownership, in order to improve operating efficiency of the memory system. Typically, the global communication bus is dedicated to one bus master during such operations by providing some indication, such as a burst attribute, to an initial portion of the transfers being burst or communicated. Such attribute is acknowledged within the system and bus arbitration control circuitry prevents a re-allocation of communication bus ownership. Once bus mastership is obtained, the current bus master keeps bus ownership for the duration of the burst transfer.
Another technique used to maintain bus ownership is for the device in control of the bus to assert a bus lock signal. A disadvantage of this technique is that any other critical interrupt in the system is locked out from using the bus until the lock signal is relinquished. The use of special lock bits is one implementation previously used in connection with such a lock signal.
Other known systems specify that burst transfers are interruptible and require that an interrupted burst transfer be reinitiated by the interrupted bus master once bus ownership is regained. A disadvantage of such a technique is the interrupted bus master must rebuild the bus transfer sequence, thus lowering overall system efficiency and adding complexity to the bus protocol.
In some special circumstances the length of a cache memory line fill may exceed the maximum required latency of a time-critical alternate bus master. Although the frequency of occurrence for this type of interruption is generally low, such alternate bus masters may require immediate access to the bus. For such situations, it is critical that the current burst sequence be temporarily interrupted and then resumed although such interruption of an existing burst transfer will assuredly lower the efficiency of the memory system and the processor associated with the current burst transfer.